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Introducing the IC Layout Security competition, new for CSAW'21.


Securing modern electronics is an important but tough challenge that requires efforts all the way from software applications down to the hardware. For the design, manufacturing, and deployment of integrated circuits (ICs), there are numerous companies and partners involved within complex and world-wide supply chains – ICs run through many hands, and some of those may be acting with malicious intent.


Participants of this newly introduced competition will focus on the final frontier for securing modern electronics – the physical layout of ICs. Acting as security engineers, participating teams will first evaluate and then fix the vulnerability of IC layouts for various attacks, like insertion of malicious circuitry in security-critical modules by untrusted design or manufacturing companies, or probing of critical modules by adversaries in the field at run-time.


This competition is open to both undergraduate and graduate-level students from around the world.

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Competition Details

competition timeline

16 August 2021
11 October 2021
15 October 2021
15 October - 5 November 2021
10 - 12 November 2021*
Submission Phase Opens
Extended Submission Deadline
Finalist Notification
Final Round Competition
CSAW Conference & Virtual Final Presentations

*These dates are for interactive, virtual presentations, to be scheduled with finalist teams in advance.

competition organizers

IC Layout Security is organized by Dr. Johann Knechtel (NYU Abu Dhabi), ECE PhD student, Jitendra Bhandari (NYU Tandon), and MS Computer Engineering student, Jayanth Gopinath (NYU Tandon). 

Email the Organizers

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