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Logic Locking is a revolutionary technique for protecting Intellectual Property of Integrated Circuits from myriad security threats, such as reverse engineering, overbuilding, piracy, and hardware Trojan insertion. In this student-led Logic Locking Conquest Challenge, participants will attempt to attack designs locked with state-of-the-art methods. This year's challenge emphasizes the assessment of large designs (large IPs, large "keys"). Can you find out what the keys are or what the IPs do?
In previous years, CSAW LL has featured FPGA-based Redaction, Sequential Locking/Obfuscation, and SAT-resilient locking.
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